Representative Work of Thomas Leffert

Patent No.	Description
6,308,282	Fault-Tolerant Networking
6,304,504	Methods and Systems for Alternate Bitline Stress Testing
6,304,488	Current Limiting Negative Switch Circuit
6,292,387	Selective Device Coupling
6,288,419	Low-R Gate Flash Memory
6,275,446	Clock Generation Circuits and Methods
6,266,066	Shadowbox Input of Illumination Information
6,211,659	Cascode Circuits in Dual-Vt, BiCMOS and DTMOS Technologies
6,191,663	Echo Reduction on Bit-Serial, Multi-Drop Bus
6,172,893	DRAM with Intermediate Storage Cache and Separate Read and Write I/O
6,104,650	Sacrifice Read Test Mode